DSP56311VL150

Product Summary

The Freescale DSP56311VL150 is a 24-Bit Digital Signal Processor. It supports network applications with general filtering operations. The Enhanced Filter Coprocessor (EFCOP) executes filter algorithms in parallel with core operations enhancing signal quality with no impact on channel throughput or total channels supported. The result is increased overall performance. Like the other DSP56300 family members, the DSP56311VL150 uses a high-performance, single-clock-cycle-per- instruction engine (DSP56000 code-compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA) controller (see Figure 1). The DSP56311VL150 performs at up to 150 million multiply-accumulates per second (MMACS), attaining up to 300 MMACS when the EFCOP is in use. It operates with an internal 150 MHz clock with a 1.8 volt core and independent 3.3 volt input/output (I/O) power. The applications of the DSP56311VL150 include Wireless and wireline infrastructure applications, Multi-channel wireless local loop systems, DSP resource boards, High-speed modem banks, IP telephony.

Parametrics

DSP56311VL150 absolute maximum ratings: (1)Supply Voltage: –0.1 to 2.0 V; (2)Input/Output Supply Voltage: –0.3 to 4.0 V; (3)All input voltages: GND – 0.3 to VCCQH + 0.3 V; (4)Current drain per pin excluding VCC and GND: 10 mA; (5)Operating temperature range: –40 to +100 ℃; (6)Storage temperature: –55 to +150 ℃.

Features

DSP56311VL150 features: (1)High-Performance DSP56300 Core: Up to 150 million multiply-accumulates per second (MMACS) (300 MMACS using the EFCOP in filtering applications) with a 150 MHz clock at 1.8 V core and 3.3 V I/O, Object code compatible with the DSP56000 core with highly parallel instruction set; (2)Enhanced Filter Coprocessor (EFCOP): Internal 24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core, Operation at the same frequency as the core (up to 150 MHz); (3)Internal Peripherals: Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs; (4)Internal Memories: 192-24-bit bootstrap ROM, 128 K-24-bit RAM total.

Diagrams